1. Field of the Invention
The present invention is related to a display device, and more particularly, to a liquid crystal display device having bi-direction voltage stabilization mechanism.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, thin appearance and low power consumption, have gradually replaced traditional cathode ray tube display (CRT) devices and widely used in electronic devices such as notebook computers, personal digital assistants (PDAs), flat panel TVs or mobile phones. Traditional LCD devices display images by driving the pixels of the panel using external driving chips. In order to reduce the number of devices and to lower manufacturing cost, gate on array (GOA) technique has been developed, in which gate drivers are directly fabricated on the panel where the pixels are disposed.
Reference is made to FIG. 1 for a top-view diagram of a related art LCD device 100. The LCD device 100, fabricated using GOA technique, includes a display area 180 and a non-display area 190. A shift register 110, a source driver 130, a clock generator 140 and a power supply 150 are disposed in the non-display area 190 for driving the pixels (not shown in FIG. 1) in the display area 180 in order to display images.
Reference is made to FIG. 2 for a simplified block diagram of the LCD device 100. FIG. 2 merely depicts a partial structure of the LCD device 100, including a plurality of gate lines GL(1)˜GL(N) disposed in the display area 180, as well as the shift register 110, the clock generator 140, and the power supply 150 disposed in the non-display area 190. The clock generator 140 can provide a start pulse signal VST and clock signals CLK1-CLKm for operating the shift register 110. The power supply 150 can provide a bias voltage VSS for operating the shift register 110. The shift register 110 includes a plurality of serially-coupled shift register units SR(1)-SR(N), which include pulse generators PG(1)-PG(N) and low level stabilizer LLS(1)-LLS(N), respectively. The output ends of the shift register units SR(1)-SR(N) are respectively coupled to the first ends L(1)-L(N) of the corresponding gate lines GL(1)-GL(N). Based on the clock signals CLK1-CLKm and the start pulse signal VST, the shift register 110 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) via the shift register units SR(1)-SR(N), respectively.
Reference is made to FIG. 3 for a diagram illustrating a related art nth-stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N), wherein n is an integer between 1 and N. The shift register unit SR(n) includes a pulse generator PG(n) and a low level stabilizer LLS(n). The input end of the shift register unit SR(n) is coupled to the output end of a prior-stage shift register unit SR(n−1). The output end of the shift register unit SR(n) is coupled to the first end L(n) of the gate line GL(n).
The pulse generators PG(n), including transistors T1, T2, T9 and T10, can generate gate driving signal GS(n) based on the clock signal CLKn and the gate driving signal GS(n−1) transmitted from the prior-stage shift register unit SR(n−1). The low level stabilizer LLS(n) includes transistors T3, T4 and T11-T14. The transistors T11-T14 form a pull-down control circuit 11 which can output control signals to the gates of the transistors 13 and T4 based on the clock signal CLKn and the voltage level of the node Q(n). Therefore, based on respective gate voltages, the transistor T3 can control the signal transmission path between the node Q(n) and the low-level bias voltage VSS, while the transistor T4 can control the signal transmission path between the first end L(n) of the gate line GL(n) and the low-level bias voltage VSS.
As shown FIG. 1, the pulse generator PG(n) and the low level stabilizer LLS(n) of the shift register unit SR(n) are both disposed in the non-display area 190 and on the same side with respect to the display area 180. During the output period of the shift register unit SR(n), the gate line GL(n) of the related art LCD device 100 receives the gate driving signal GS(n) generated by the pulse generators PG(n) at the first end L(n); during other periods excluding the output period of the shift register unit SR(n), the voltage level of the gate line GL(n) in the related art LCD device 100 is maintained using the transistors T3 and T4 of the low-level stabilizer LLS(n). The related art LCD device 100 adopts a uni-directional voltage stabilizing structure, in which the node Q(n) is pulled down to the low-level bias voltage VSS via the turned-on transistor T3, thereby turning off the transistor T2 and preventing the first end L(n) of the gate line GL(n) from being influenced by the clock signal CLKn. Meanwhile, the first end L(n) of the gate line GL(n) is pulled down to the low-level bias voltage VSS via the turned-on transistor T4, thereby keeping the gate driving signal GS(n) at the low level from the signal input side.
In the driving circuits of an LCD device, the channel width/length ratio of a transistor is determined based on how much driving is required. A transistor having a larger channel width/length ratio provides higher driving capability, but occupies larger circuit space. The pull-down circuit 11 generally adopts the transistors T11-T14 with small channel width/length ratio, which can provide sufficient driving for generating the control signals of the transistor T3. Therefore, when performing miniaturization or rim reduction in the LCD device, the major impact on panel size is mainly contributed by the channel width/length ratios W/L1˜W/L4 of the transistors T1-T4.
In the related art LCD device 100, since the pulse generator PG(n) receives the input signal using the transistor T1 and outputs the gate driving signal GS(n) for driving the gate line GL(n) using the transistor T2, the transistor T2 needs to provide much higher driving capability than the transistor T1. Since the low-level stabilizer LLS(n) maintains the voltage level of the node Q(n) using the transistor T3 and maintains the voltage level of the entire output using the transistor T4, the transistor T4 needs to provide much higher driving capability than the transistor T3. Generally, W/L1 is about 300, W/L2 is about 2000, W/L3 is about 40, and W/L4 is about 300. The capacitor CD in FIG. 3 may be a parasitic capacitor of the largest transistor T1.
As shown in FIG. 1, the non-display area around the display area includes dummy space regardless of the position of the driving circuits. The related art LCD device 100 adopts a uni-directional driving and stabilizing structure, in which the pulse generator PG(n) and the low-level stabilizer LLS(n) of the shift register unit SR(n) are both disposed in the dummy space of the non-display area 190 at the same side with respect to the display area 180. Since the transistors T1-T4 occupy large circuit space, rim reduction cannot be effectively performed on the LCD device 100.